This invention relates to a semiconductor switch, and more particularly, to a latching semiconductor switch comprised of a gate turn-off thyristor and a load transistor coupled in a Darlington configuration.
Various industrial control applications often require switching of large currents. The high speed and efficiency of semiconductors make such devices desirable for such switching applications. Heretofore, discrete transistors and gate turn-off thyristors have been employed as switching devices but not without limitations on each respective device. While a conventional transistor can provide high frequency switching of moderate currents, it requires the presence of a continuous, minimum amplitude base current to remain conductive. The necessity of continuous base current for sustained transistor conduction often requires a separate DC supply which usually must be isolated from other circuitry. Darlington transistors provide additional power handling capability but do not eliminate the need for continuous base drive current in order to remain conductive.
Four-layer PNPN semiconductor switching devices of the gate turn-off thyristor type allow a semiconductor switching device to be realized which does not need a continuous base current to remain conductive. Once rendered conductive by a positive current pulse, the gate turn-off thyristor remains conductive until a negative gate current pulse is applied to turn the device off. While a gate turn-off thyristor does not require a continuous gate current to remain conductive, substantial negative gate current, typically on the order of 10 to 20 percent of the thyristor anode current, must be applied to pulse the device out of conduction. This results in the thyristor turn-off gain (the ratio of thyristor anode current to thyristor gate current at turn-off) being relatively low, which renders the thyristor unsuitable for applications where high turn-off gain is required.
It has been proposed to combine the gate turn-off thyristor and the conventional transistor in a Darlington configuration to yield a latching semiconductor switch having high turn-off gain. F. E. Gentry, in U.S. Pat. No. 3,265,909 issued on Aug. 9, 1966 and assigned to the assignee of the present invention has described and claimed such a semiconductor switch configured in a Darlington arrangement with the gate turn-off thyristor supplying base drive to the transistor.
The latching Darlington configuration of Gentry is, however, subject to the disadvantage that steeply increasing voltage transients appearing across the collector-emitter portion of the load transistor can falsely trigger the thyristor and hence the latching Darlington configuration into conduction even though the voltage transients are of a magnitude less than the breakover voltage of the gate turn-off thyristor. This phenomenon of thyristor conduction degradation due to steeply increasing voltage transients is termed the "dv/dt effect" and is more fully described on pages 221 through 222 of the text, Semiconductor Power Devices by Sorab K. Ghandi, published by John Wiley and Sons, 1977.
To improve the dv/dt capability of a latching Darlington transistor such as the type described in the aforementioned Gentry patent, I Ohhinnata, in U.S. Pat. No. 4,112,315 issued Sept. 5, 1978 provides a resistance coupled between the gate and cathode of the four layer PNPN semiconductor. This resistance serves to drop the magnitude of any transient voltage pulses appearing across the latching Darlington transistor at turn-off. Steeply increasing high voltage transients may still retrigger the Ohhinnata latching Darlington transistor into conduction, rendering such a device suitable for small signal circuit applications only.
The present invention concerns a latching semiconductor switch having high turn-off gain and increased dv/dt capability for preventing premature device conduction.